Dual metal wrap-around contacts for semiconductor devices

ABSTRACT

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 16/803,987, filed Feb. 27, 2020, currently granted as U.S. Pat.No. 11,374,101, which claims priority to U.S. Provisional PatentApplication Ser. No. 62/812,103 filed on Feb. 28, 2019, and U.S.Provisional Patent Application Ser. No. 62/812,120 filed on Feb. 28,2019. All of these applications and patents are incorporated herein byreference, including their specification.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods formanufacturing those devices, and more particularly, to low-resistivitydual metal wrap-around contacts for aggressively scaled devices.

BACKGROUND OF THE INVENTION

Current and future generations of metal-oxide-semiconductor field effecttransistors (MOSFETs) require tight control of parasitic capacitancewhile simultaneously optimizing metal-semiconductor contact resistance.Source and drain contact resistivity is one of the critical parameterthat needs to be addressed to improve performance of scaled FinFETs andsilicon nanowire/nanosheet devices. The adoption of ultra-thintransistor body structures such as FinFET and fully depletedsilicon-on-insulator (FDSOI) has exacerbated the problem of contactresistance for logic manufacturing.

SUMMARY OF THE INVENTION

A semiconductor device and a method for forming a semiconductor deviceis described in several embodiments of the invention.

According to one embodiment, a semiconductor device includes a firstraised feature in a n-type channel field effect transistor (NFET) regionon a substrate, a first n-type doped epitaxial semiconductor materialgrown on the first raised feature, the first n-type doped epitaxialmaterial having a first upward facing surface and a first downwardfacing surface, a first contact metal on the first downward facingsurface, and a second contact metal on the first upward facing surface.The device further includes a second raised feature in a p-type channelfield effect transistor (PFET) region on the substrate, a second p-typedoped epitaxial semiconductor material grown on the second raisedfeature, the second p-type doped epitaxial material having a secondupward facing surface and a second downward facing surface, a thirdcontact metal on the second downward facing surface, and a fourthcontact metal on the second upward facing surface, wherein the fourthcontact metal is different from the second contact metal. In oneembodiment, the first contact metal contains the same metal as the thirdcontact metal. In another embodiment, the first contact metal isdifferent from the third contact metal.

According to one embodiment, a method of forming a semiconductor deviceincludes providing a first raised feature in a n-type channel fieldeffect transistor (NFET) region on a substrate, growing a first n-typedoped epitaxial semiconductor material on the first raised feature, thefirst n-type doped epitaxial material having a first upward facingsurface and a first downward facing surface, forming a first contactmetal on the first downward facing surface, forming a second contactmetal on the first upward facing surface, providing a second raisedfeature in a p-type channel field effect transistor (PFET) region on thesubstrate. The method further includes growing a second p-type dopedepitaxial semiconductor material on the second raised feature, thesecond p-type doped epitaxial material having a second upward facingsurface and a second downward facing surface, forming a third contactmetal on the second downward facing surface, and forming a fourthcontact metal on the second upward facing surface, wherein the fourthcontact metal is different from the second contact metal. In oneembodiment, the first contact metal contains the same metal as the thirdcontact metal. In another embodiment, the first contact metal isdifferent from the third contact metal.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A-1AA schematically show through cross-sectional views a methodof forming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention;

FIGS. 2A-2C schematically show through cross-sectional views a method offorming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention;

FIGS. 3A-3C schematically show through cross-sectional views a method offorming a semiconductor device containing dual wrap-around contactsaccording to an embodiment of the invention;

FIGS. 4A-4Y schematically show through cross-sectional views a method offorming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention;

FIGS. 5A-5C schematically show through cross-sectional views a method offorming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention; and

FIGS. 6A-6C schematically show through cross-sectional views a method offorming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

A semiconductor device and a method for forming a semiconductor deviceis described in several embodiments of the invention. Maximizing thecontact area in FinFET structures can be achieved by creating a contactthat wraps around the fin or by growing faceted epitaxial contacts, andthen wrapping metal around the faceted epitaxial contacts. In order toreduce spreading resistance in FinFET structures, wrap around contact(WAC) structures use metal-semiconductor contacts with an increasedarea.

FIGS. 1A-1AA schematically show through cross-sectional views a methodof forming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention. FIG. 1Aschematically shows a substrate 1 containing a base layer 100 that formsa raised feature 105 in a NFET region 101 and a raised feature 107 in aPFET region 103. The base layer 100 can consist of Si and and a shallowtrench isolation (STI) region 104 separating the NFET region 101 and thePFET region 103 can include silicon oxide (SiO₂). The substrate 1further contains three patterned film stacks in each of the NFET region101 and the PFET region 103. The patterned film stacks each include asacrificial SiO₂ film 110, a dummy polycrystalline-silicon (poly-Si)film 112, a SiO₂ hard mask 114, and a silicon nitride (SiN) hard mask116. The number of the patterned film stacks in FIG. 1A is exemplary andany number of patterned film stacks may be used. The patterned films maybe formed using conventional lithography and etching methods.

FIG. 1B shows a low-k gate spacer layer 118 that is conformallydeposited on the substrate 1, where the low-k gate spacer layer 118 can,for example, include SiCO or SiBCN materials. FIG. 1C shows an organiclayer 132 that is deposited and patterned using a patterned photoresistlayer 134 to cover the NFET region 101. In some examples, the organiclayer 132 can include an organic planarization layer (OPL) or an organicdielectric layer (ODL). FIG. 1C further shows the substrate 1 followinga reactive ion etching process (RIE) that removes horizontal portions ofthe low-k gate spacer layer 118 in the PFET region 103, while the low-kspacer layer 118 in the NFET region 101 is protected from the RIE by theorganic layer 132. The remaining vertical portions of the low-k gatespacer layer 118 form sidewall spacers on the patterned film stacks inthe PFET region 103. FIG. 1D shows the substrate 1 following removal ofthe organic layer 132 and the patterned photoresist layer 134 from theNFET region 101.

FIG. 1E shows the substrate 1 following selective deposition of a secondp-type doped epitaxial semiconductor material 136 on exposed surfaces ofthe second raised feature 107 (e.g., Si fin) in the PFET region 103. Thesecond p-type doped epitaxial semiconductor material 136 can, forexample, contain p-type Si that includes boron-doped silicon (Si:B) orp-type silicon germanium that includes boron-doped silicon germanium(SiGe:B). The selective epitaxial deposition results in the secondp-type doped epitaxial semiconductor material 136 being faceted andwrapping around the second raised feature 107, where the second p-typedoped epitaxial semiconductor material 136 has upward facing surfacesand downward facing surfaces. Si:B may be selectively deposited usingSiH₄, Si₂H₆, or SiH₂Cl₂ and BH₃ or B₂H₆. SiGe:B may be selectivelydeposited using SiH₄, Si₂H₆, or Si₂H₂Cl₂ and GeH₄ and BH₃ or B₂H₆.

FIG. 1F shows the substrate 1 following conformal deposition of a SiNliner 130 over the raised and recessed features of the substrate 1, andFIG. 1G shows an organic layer 120 that is patterned to cover the PFETregion 103 using a patterned photoresist layer 122. In some examples,the organic layer 120 can include an OPL or an ODL. FIG. 1G furthershows the substrate 1 following a RIE that removes horizontal portionsof the SiN liner 130 in the NFET region 101, while the SiN liner 130 inthe PFET region 103 is protected from the RIE. The remaining verticalportions of the SiN liner 130 form sidewall spacers on the patternedfilm stacks in the NFET region 101. FIG. 1H shows the substrate 1following removal of the organic layer 120 and the patterned photoresistlayer 122 from the PFET region 103.

FIG. 1I shows the substrate 1 following selective deposition of a firstn-type doped epitaxial semiconductor material 124 on exposed surfaces ofthe first raised feature 105 (e.g., Si fin) in the NFET region 101. Thefirst n-type doped epitaxial semiconductor material 124 can, forexample, contain n-type Si that includes phosphor-doped silicon (Si:P)or arsenic-doped silicon (Si:As). The selective epitaxial depositionresults in the first doped epitaxial semiconductor material 124 wrappingaround the first raised feature 105, where the first n-type dopedepitaxial semiconductor material 124 has upward facing surfaces anddownward facing surfaces. Si:P may be selectively deposited using SiH₄,Si₂H₆, or SiH₂Cl₂ and PH₃. Si:As may be selectively deposited usingSiH₄, Si₂H₆ or SiH₂Cl₂ and AsH₃. Exemplary substrate temperatures canrange from about 400° C. to about 800° C.

FIG. 1J shows the substrate 1 following removal of the SiN liner 130from the substrate 1. FIG. 2A shows a cross-sectional view along theline A-A′ of FIG. 1J that includes a first downward facing surface 111and a first upward facing surface 113 of the first n-type dopedepitaxial semiconductor material 124. Similarly, FIG. 3A shows across-sectional view along the line B-B′ of FIG. 1J that includes asecond downward facing surface 115 and a second upward facing surface117 of the second p-type doped epitaxial semiconductor material 136. Aliner 102 separates the STI 104 from the first raised feature 105 andfrom the second raised feature 107.

FIG. 1K shows the substrate 1 following deposition of a first metallayer 138 on the first n-type epitaxial semiconductor material 124 andon the second p-type doped epitaxial semiconductor material 136. In oneexample, the first metal layer 38 can include titanium (Ti) metal orruthenium (Ru) metal. Ti metal deposition can be achieved using TiCl₄gas flow and pulsed RF plasma. Ru metal deposition can be achieved usinga process gas containing Ru₃(CO)₁₂ and CO. The first metal layer 138wraps around the first n-type doped epitaxial semiconductor material 124and the second p-type doped epitaxial semiconductor material 136. FIG.2B shows a cross-sectional view along the line C-C′ of FIG. 1K thatincludes the first metal layer 138 on the first downward facing surface111 and on the first upward facing surface 113 of the first n-type dopedepitaxial semiconductor material 124. Similarly, FIG. 3B shows across-sectional view along the line D-D′ of FIG. 1K that includes thefirst metal layer 138 on the second downward facing surface 115 and onthe second upward facing surface 117 of the second p-type dopedepitaxial semiconductor material 136.

FIG. 1L shows the substrate 1 following conformal deposition of a SiNliner 149 over the raised and recessed features of the substrate 1, andFIG. 1M shows the substrate 1 following blanket deposition of a gap-filloxide film 150, were the gap-fill oxide film 150 may be deposited usinga flowable oxide and a SiH₄-based oxide, for example. FIG. 1N shows thesubstrate 1 following a planarization process that stops on the SiN hardmask 116. In one example, the planarization process can include chemicalmechanical polishing (CMP).

FIG. 1O shows the substrate 1 following removal of the patterned filmstacks and replacement with a high-k layer 144 and a metal gate layer146. FIG. 1P shows the substrate 1 following deposition of a SiN liner148 and an interlayer dielectric (ILD) 160 on the SiN liner 148.Thereafter, as shown in FIG. 1Q, a self-aligned contact etching processis performed to form recessed features 152 down to the first metal layer138 in the NFET region 101 and the PFET region 103. FIG. 1R shows thesubstrate following an etching process that etches through the firstmetal layer 138 and stops on the first n-type doped epitaxialsemiconductor material 124 and the second p-type doped epitaxialsemiconductor material 136.

Thereafter, as shown in FIG. 1S, a second metal layer 161 (e.g., a Tilayer) is deposited in the recessed features 152 and a titanium nitride(TiN) layer 154 is conformally deposited on the substrate 1, includingin the recessed features 152. In some examples, the second metal layer161 may be annealed to react to form a metal silicide (e.g., TiSi_(x)).In one example, the TiN layer 154 can have a thickness of less thanabout 3 nm. FIG. 1T shows the substrate 1 following blanket depositionof a tungsten (W) metal layer 156 that fills the recess features 152.Thereafter, as shown in FIG. 1U, the W metal layer 156 is planarizeddown to the TiN layer 154.

FIG. 1V shows an organic layer 131 that is deposited and patterned tocover the NFET region 101 using a patterned photoresist layer 133. Insome examples, the organic layer 131 can include an OPL or an ODL. FIG.1W further shows the substrate 1 following a RIE process that removesthe TiN layer 154, the W metal layer 156, and the second metal layer 161from the PFET region 103, while the TiN layer 154, the W metal layer156, and the second metal layer 161 in the NFET region 101 are protectedfrom the RIE by the organic layer 131. FIG. 1X shows the substrate 1following removal of the organic layer 131 and the patterned photoresistlayer 133 from the NFET region 101.

FIG. 1Y shows the substrate 1 following selective deposition of a thirdmetal layer 162 on the second p-type doped epitaxial semiconductormaterial 136 in the recessed features 152 and a blanked deposition of aTiN layer 158. In some examples, the third metal layer 162 can includeruthenium (Ru) metal or nickel platinum (NiPt). FIG. 1Z shows thesubstrate 1 following blanket deposition a W metal layer 164 that fillsthe recessed features 152 in the PFET region 103.

Thereafter, as shown in FIG. 1AA, the W metal layer 164 is planarizeddown to the TiN layer 154. FIG. 2C shows a cross-sectional view alongthe line E-E′ of FIG. 1AA that includes the first metal layer 138 (firstcontact metal) on the first downward facing surface 111 and the secondmetal layer 161 (second contact metal) on the first upward facingsurface 113. Similarly, FIG. 3C shows a cross-sectional view along theline F-F′ of FIG. 1AA that includes the first metal layer 138 (thirdcontact metal) on the second downward facing surface 115 and the thirdmetal layer 162 (fourth contact metal) on the second upward facingsurface 117.

FIGS. 4A-4Y schematically show through cross-sectional views a method offorming a semiconductor device containing dual metal wrap-aroundcontacts according to an embodiment of the invention. Substrate 1 inFIG. 1D has been reproduced as substrate 4 in FIG. 4A.

FIG. 4B shows the substrate 4 following selective deposition of a secondp-type doped epitaxial semiconductor material 137/136 on exposedsurfaces of the second raised feature 107 (e.g., Si fin) in the PFETregion 103. The second p-type doped epitaxial semiconductor material137/136 can be p-type and can, for example, contain boron-dopedgermanium (Ge:B) on boron-doped silicon germanium (SiGe:B). Theselective epitaxial deposition results in the second p-type dopedepitaxial semiconductor material 137/136 being faceted and wrappingaround the second raised feature 107, where the second p-type dopedepitaxial semiconductor material 137/136 has upward facing surfaces anddownward facing surfaces. Ge:B may be selectively deposited using GeH₄and BH₃ or B₂H₆. SiGe:B may be selectively deposited using SiH₄, Si₂H₆,or SiH₂Cl₂, GeH₄ and BH₃ or B₂H₆. FIG. 6A shows a cross-sectional viewalong the line A-A′ of FIG. 4B that includes a first downward facingsurface 125 and a first upward facing surface 127 of the secondepitaxial semiconductor material 137/136.

FIG. 4C shows the substrate 4 following deposition of a fourth metallayer 139 on the second p-type doped epitaxial semiconductor material137/136. In one example, the fourth metal layer 139 can includeruthenium (Ru) metal. Ru metal deposition can be achieved using aprocess gas containing Ru₃(CO)₁₂ and CO. The fourth metal layer 139wraps around the second p-type doped epitaxial semiconductor material137/136.

FIG. 4D shows the substrate 4 following conformal deposition of a SiNliner 141 over the raised and recessed features of the substrate 4, andFIG. 4E shows an organic layer 120 that is patterned to cover the PFETregion 103 using a patterned photoresist layer 122. In some examples,the organic layer 120 can include an OPL or an ODL. FIG. 4E furthershows the substrate 4 following a RIE that removes horizontal portionsof the SiN liner 141 in the NFET region 101, while the SiN liner 141 inthe PFET region 103 is protected from the RIE. The remaining verticalportions of the SiN liner 141 form sidewall spacers on the patternedfilm stacks in the NFET region 101. FIG. 4F shows the substrate 4following removal of the organic layer 120 and the patterned photoresistlayer 122 from the PFET region 103.

FIG. 4G shows the substrate 4 following selective deposition of a firstn-type doped epitaxial semiconductor material 124 on exposed surfaces ofthe first raised feature 105 (e.g., Si fin) in the NFET region 101. Thefirst n-type doped epitaxial semiconductor material 124 can, forexample, contain n-type doped Si that includes phosphor-doped silicon(Si:P) or arsenic-doped silicon (Si:As). The selective epitaxialdeposition results in the first n-type doped epitaxial semiconductormaterial 124 wrapping around the first raised feature 105, where thefirst n-type doped epitaxial semiconductor material 124 has upwardfacing surfaces and downward facing surfaces. Si:P may be selectivelydeposited using SiH₄, Si₂H₆ or SiH₂Cl₂ and PH₃. Si:As may be selectivelydeposited using SiH₄, Si₂H₆ or SiH₂Cl₂ and AsH₃. FIG. 5A shows across-sectional view along the line C-C′ of FIG. 4G that includes afirst downward facing surface 121 and a first upward facing surface 123of the first n-type doped epitaxial semiconductor material 124.

FIG. 4H shows the substrate 4 following deposition of a fifth metallayer 126 on the first n-type doped epitaxial semiconductor material124. In one example, the fifth metal layer 126 can include ruthenium(Ru) metal. Ru metal deposition can be achieved using a process gascontaining Ru₃(CO)₁₂ and CO. The fifth metal layer 126 wraps around thefirst n-type doped epitaxial semiconductor material 124. FIG. 5B shows across-sectional view along the line D-D′ of FIG. 4H that includes thefirst metal layer 126 on the first downward facing surface 121 and onthe first upward facing surface 123 of the first n-type doped epitaxialsemiconductor material 124. FIG. 4I shows the substrate 4 followingremoval of the SiN liner 141 from the substrate 4.

FIG. 4J shows the substrate 4 following conformal deposition of a SiNliner 143 over the raised and recessed features of the substrate 4, andFIG. 4K shows the substrate 4 following blanket deposition of a gap-filloxide film 150, were the gap-fill oxide film 150 may be deposited usinga flowable oxide and a SiH₄-based oxide, for example. FIG. 4L shows thesubstrate 1 following a planarization process that stops on the SiN hardmask 116. In one example, the planarization process can include CMP.

FIG. 4M shows the substrate 4 following removal of the patterned filmstacks and replacement with a high-k layer 144 and a metal gate layer146. FIG. 4N shows the substrate 4 following deposition of a SiN liner148 and an interlayer dielectric (ILD) 160 on the SiN liner 148.Thereafter, as shown in FIG. 40, a self-aligned contact etching processis performed to form recessed features 152 down to the fourth metallayer 139 in the PFET region 103 and the fifth metal layer 126 in theNFET region 101. FIG. 4P shows the substrate 1 following an etchingprocess that etches through the fourth metal layer 139 and stops on thesecond p-type doped epitaxial semiconductor material 137/136, and etchesthrough the fifth metal layer 126 and stops on the first n-type dopedepitaxial semiconductor material 124.

Thereafter, as shown in FIG. 4Q, a sixth metal layer 168 (e.g., a Tilayer) is deposited in the recessed features 152 and a titanium nitride(TiN) layer 154 is conformally deposited on the substrate 4, includingin the recessed features 152. In some examples, the sixth metal layer168 may react to form a metal silicide (e.g., TiSi_(x)). In one example,the TiN layer 154 can have a thickness of less than about 3 nm. FIG. 4Rshows the substrate 4 following blanket deposition of a tungsten (W)metal layer 164 that fills the recess features 152. Thereafter, as shownin FIG. 4S, the W metal layer 164 is planarized down to the TiN layer154.

FIG. 4T shows an organic layer 131 that is deposited and patterned tocover the NFET region 101 using a patterned photoresist layer 133. Insome examples, the organic layer 131 can include an OPL or an ODL. FIG.4U further shows the substrate 4 following a RIE process that removesthe TiN layer 154, the W metal layer 164, and the sixth metal layer 168from the PFET region 103, while the TiN layer 154, the W metal layer 164and the sixth metal layer 168 in the NFET region 101 are protected fromthe RIE by the organic layer 131. FIG. 4V shows the substrate 1following removal of the organic layer 131 and the patterned photoresistlayer 133 from the NFET region 101.

FIG. 4W shows the substrate 4 following selective deposition of aseventh metal layer 169 (e.g., a Ru layer or a NiPt layer) on the secondp-type doped epitaxial semiconductor material 137/136 in the recessedfeatures 152 and a blanked deposition of a TiN layer 158. FIG. 4X showsthe substrate 1 following blanket deposition a W metal layer 166 thatfills the recess features 152 in the PFET region 103. Thereafter, asshown in FIG. 4Y, the W metal layer 166 is planarized.

FIG. 5C shows a cross-sectional view along the line E-E′ of FIG. 4Y thatincludes the fifth metal layer 126 (first contact metal) on the firstdownward facing surface 121 and the sixth metal layer 168 (secondcontact metal) on the first upward facing surface 123. Similarly, FIG.6C shows a cross-sectional view along the line F-F′ of FIG. 4Y thatincludes the fourth metal layer 139 (third contact metal) on the seconddownward facing surface 125 and the seventh metal layer 169 (fourthcontact metal) on the second upward facing surface 127.

A plurality of embodiments for low-resistivity dual metal wrap-aroundcontacts in aggressively scaled devices have been described. Theforegoing description of the embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. This description and the claims following include terms thatare used for descriptive purposes only and are not to be construed aslimiting. Persons skilled in the relevant art can appreciate that manymodifications and variations are possible in light of the aboveteaching. Persons skilled in the art will recognize various equivalentcombinations and substitutions for various components shown in theFigures. It is therefore intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto.

What is claimed is:
 1. A method of forming a semiconductor device, themethod comprising: providing a first raised feature in a n-type channelfield effect transistor (NFET) region on a substrate; growing a firstn-type doped epitaxial semiconductor material on the first raisedfeature, the first n-type doped epitaxial semiconductor material havinga first upward facing surface and a first downward facing surface;forming a first contact metal on the first downward facing surface;forming a second contact metal on the first upward facing surface;providing a second raised feature in a p-type channel field effecttransistor (PFET) region on the substrate; growing a second p-type dopedepitaxial semiconductor material on the second raised feature, thesecond p-type doped epitaxial semiconductor material having a secondupward facing surface and a second downward facing surface; forming athird contact metal on the second downward facing surface; and forming afourth contact metal on the second upward facing surface, wherein thefourth contact metal is different from the second contact metal, and thefirst contact metal is the different from the third contact metal. 2.The method of claim 1, wherein the first n-type doped epitaxialsemiconductor material contains Si:P or Si:As, the first contact metalcontains Ru or Ti, and the second contact metal contains Ti or TiSi_(x).3. The method of claim 1, wherein the second p-type doped epitaxialsemiconductor material contains Si:B or SiGe:B, the third contact metalcontains Ru or Ti, and the fourth contact metal contains NiPt or Ru. 4.The method of claim 1, wherein the first and second raised features arefins that extend through a shallow trench isolation (STI) layer.
 5. Themethod of claim 1, wherein forming the first contact metal on the firstdownward facing surface and forming the second contact metal on thefirst upward facing surface includes: conformally depositing the firstcontact metal on the first upward facing surface and on the firstdownward facing surface; removing the first contact metal from the firstupward facing surface; and depositing the second contact metal on thefirst upward facing surface.
 6. The method of claim 1, wherein formingthe third contact metal on the second downward facing surface andforming the fourth contact metal on the second upward facing surfaceincludes: conformally depositing the third contact metal on the secondupward and downward facing surfaces; removing the third contact metalfrom the second upward facing surface; and depositing the fourth contactmetal on the second upward facing surface.
 7. A method of forming asemiconductor device, the method comprising: providing a first raisedfeature in a n-type channel field effect transistor (NFET) region on asubstrate; growing a first n-type doped epitaxial semiconductor materialon the first raised feature, the first n-type doped epitaxialsemiconductor material having a first upward facing surface and a firstdownward facing surface; forming a first contact metal on the firstdownward facing surface; forming a second contact metal on the firstupward facing surface; providing a second raised feature in a p-typechannel field effect transistor (PFET) region on the substrate; growinga second p-type doped epitaxial semiconductor material on the secondraised feature, the second p-type doped epitaxial semiconductor materialhaving a second upward facing surface and a second downward facingsurface; forming a third contact metal on the second downward facingsurface; and forming a fourth contact metal on the second upward facingsurface, wherein the fourth contact metal is different from the secondcontact metal, the first contact metal is the different from the thirdcontact metal, the first n-type doped epitaxial semiconductor materialcontains Si:P or Si:As, the first contact metal contains Ti, and thesecond contact metal contains Ti or TiSi_(x).
 8. The method of claim 7,wherein the second p-type doped epitaxial semiconductor materialcontains Si:B or SiGe:B, the third contact metal contains Ru, and thefourth contact metal contains NiPt or Ru.
 9. The method of claim 7,wherein the first and second raised features are fins that extendthrough a shallow trench isolation (STI) layer.
 10. The method of claim7, wherein forming the first contact metal on the first downward facingsurface and forming the second contact metal on the first upward facingsurface includes: conformally depositing the first contact metal on thefirst upward facing surface and on the first downward facing surface;removing the first contact metal from the first upward facing surface;and depositing the second contact metal on the first upward facingsurface.
 11. The method of claim 7, wherein forming the third contactmetal on the second downward facing surface and forming the fourthcontact metal on the second upward facing surface includes: conformallydepositing the third contact metal on the second upward and downwardfacing surfaces; removing the third contact metal from the second upwardfacing surface; and depositing the fourth contact metal on the secondupward facing surface.
 12. A method of forming a semiconductor device,the method comprising: providing a first raised feature in a n-typechannel field effect transistor (NFET) region on a substrate; growing afirst n-type doped epitaxial semiconductor material on the first raisedfeature, the first n-type doped epitaxial semiconductor material havinga first upward facing surface and a first downward facing surface;forming a first contact metal on the first downward facing surface;forming a second contact metal on the first upward facing surface;providing a second raised feature in a p-type channel field effecttransistor (PFET) region on the substrate; growing a second p-type dopedepitaxial semiconductor material on the second raised feature, thesecond p-type doped epitaxial semiconductor material having a secondupward facing surface and a second downward facing surface; forming athird contact metal on the second downward facing surface; and forming afourth contact metal on the second upward facing surface, wherein thefourth contact metal is different from the second contact metal, thefirst contact metal is the different from the third contact metal, thesecond p-type doped epitaxial semiconductor material contains Si:B orSiGe:B, the third contact metal contains Ru, and the fourth contactmetal contains NiPt or Ru.
 13. The method of claim 12, wherein the firstn-type doped epitaxial semiconductor material contains Si:P or Si:As,the first contact metal contains Ti, and the second contact metalcontains Ti or TiSi_(x).
 14. The method of claim 12, wherein the firstand second raised features are fins that extend through a shallow trenchisolation (STI) layer.
 15. The method of claim 12, wherein forming thefirst contact metal on the first downward facing surface and forming thesecond contact metal on the first upward facing surface includes:conformally depositing the first contact metal on the first upwardfacing surface and on the first downward facing surface; removing thefirst contact metal from the first upward facing surface; and depositingthe second contact metal on the first upward facing surface.
 16. Themethod of claim 12, wherein forming the third contact metal on thesecond downward facing surface and forming the fourth contact metal onthe second upward facing surface includes: conformally depositing thethird contact metal on the second upward and downward facing surfaces;removing the third contact metal from the second upward facing surface;and depositing the fourth contact metal on the second upward facingsurface.